Speaker:	Abel Vanel (CEA-Saclay)
Title:	X- and gamma-ray miniature detector developments at CEA for space science and industrial applications
Date (JST):	Fri, Sep 12, 2025, 13:30 - 15:00
Place:	Seminar Room A
Abstract:	Caliste is a 3D miniature, space-qualified modular imaging spectrometer developed by CEA over the last 20 years for X- and gamma-ray photon-counting applications. Based on pixelated Schottky CdTe crystals and read out by eight full-custom IDeF-X ASICs, Caliste offers high spectral performance, low power consumption, and strong radiation tolerance. Originally designed for low-leakage current pixelated CdTe, this technology can be adapted to other sensor types, such as Silicon, and to various electrode geometries, including strip detectors. It has demonstrated high flexibility and is now used across a wide range of applications, from astrophysics to nuclear imaging. Several versions have been deployed. The first high-resolution device, Caliste-HD, features a 16×16-pixel matrix with a 625 µm pitch over a 1 cm² surface, achieving ~700 eV FWHM at 60 keV. The detector operates from 2 to 250 keV. An ultra-low-power variant (20 mW), Caliste-SO, was specifically developed for solar flare observations and has been operating continuously since 2021 onboard ESA’s Solar Orbiter/STIX, with 1.2 keV FWHM at 31 keV. The same detector also flies on the PADRE CubeSat mission led by NASA and UCB, launched in June 2025. Since 2020, Caliste-O, a more recent version with a 2 mm thick CdTe crystal, has been designed for industrial use and integrated into the SPID-X gamma camera developed with 3D PLUS, our industrial partner. It is designed to support much thicker CdZnTe sensors, with ongoing developments up to 10 mm. My work focuses on the readout system developed for the Caliste detector family, particularly in the context of the SPID-X gamma camera. I have studied and worked extensively with the existing FPGA-based acquisition architecture, including digital control of the IDeF-X ASICs via VHDL. I am currently porting this system to embedded SoC platforms, using PetaLinux and Python, with the goal of bringing data processing and analysis closer to the detector. This embedded approach enables onboard detector management (ASIC control, temperature regulation, noisy pixel rejection), individual channel self-calibration, histogram generation, and real-time reconstruction of coded-mask and Compton images. These developments mark an important step toward smart and autonomous detection systems, featuring AI capabilities. During the seminar, I will present the Caliste detector technology in detail, including ASIC properties. I will emphasize the current status of the integrated implementation. I will conclude my presentation with a brief overview of the next detector generation under development, Caliste-MC2. The latter features a much finer pitch CdTe sensor with 64×64 pixels with 250 µm pitch, designed to combine high spatial and energy resolution with advanced onboard processing capabilities.

← Back